1. Technical Field
The present invention relates to an integrated circuit (IC) including a counter circuit and a one-chip microcomputer thereof and, particularly, to an IC including a counter circuit for outputting a count end pulse every time a desired value is counted, and which is capable of reducing the number of logic elements constituting the counter circuit so that other circuits can be integrated therewith.
2. Background Art
FIG. 5 shows a conventional counter circuit 100 included in an IC. The counter circuit 100 counts clock signals and externally supplied input signals until the total number reaches a set count, and then produces a count end pulse. Reference numerals 10, 20, 30 and 40 depict a register, a counter, a counter value coincidence detection circuit and a stop circuit for stopping production of the count end pulse, respectively.
The register 10 receives a data value G from other circuits and stores it. The counter 20 receives a countable signal F such as a clock signal, a event signal input externally, increments its count and, responsive to an initializing signal E, clears its count value.
The count coincidence detection circuit 30 includes single bit coincidence detection circuits corresponding in number to the number of bits of the register 10 and hence the counter 20, although only two, 31 and 32, of them are shown, and an end signal generator circuit 33 for producing a count end signal when all detection signals are generated.
The coincidence detection circuits 31 and 32 are provided for respective digits of the counter 20 and are usually constituted with exclusive OR elements. Each exclusive OR element receives an output signal A from a Q output of a flip-flop 11 for a certain digit of the register 10 and an output signal B of 1 bit corresponding to that digit of the counter 20, and outputs the result of an exclusive OR operation performed on them as a bit coincidence detection signal C. The end signal generator circuit 33 is usually constituted with an AND gate. In FIG. 5, a negative logic input AND gate 33 is used which provides a count end pulse D when all of the exclusive OR gates 31, 32 output the coincidence signals C.
The Stop circuit 40 is constituted with a delay circuit 41 in this example and is responsive to the count end pulse D to output an initializing signal E after a certain time has elapsed from a start of output of this signal. Upon receiving the initializing signal E, the counter 20 is initialized, so that the counter value becomes different from the aimed value held in the register 10. Therefore, the output of the AND gate 33 is stopped, which determines the width of the count end pulse D by a delay time of the delay circuit 41.
The initialized counter starts again to count the signal F up to the aimed value held in the register 10, and the above mentioned operation is repeated, so that the count end pulse D is generated whenever the counter counts the signals F corresponding in number to the aimed value. Such a counter circuit is included in an IC and used as a frequency divider and/or a timer, etc.
Usually, the coincidence detection circuit is constituted with the exclusive OR gates 31 and 32, each being constituted with a NOR gate 31c for receiving the A and B outputs, an AND gate 31b for receiving the A and B outputs and a NOR gate responsive to outputs of the NOR gate 31c and the AND gate 31b for providing the coincidence signal c. The exclusive OR gate 31 may be realized with 10 CMOS transistors, which means that the number of transistors is larger than that of an AND or an OR gate, which can be realized with several transistors.
Further, in such a counter circuit, the number of the coincidence detection circuits must correspond to the number of the digits of the aimed value. Therefore, the coincidence detection circuit 30 of this kind of counter circuit 100 occupies a large percentage of the area on a chip, which means that other circuits cannot be integrated on the same chip.